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Features
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Single Voltage Operation Read/Write: 2.65V - 3.6V 2.7V - 3.6V Read/Write Access Time - 70 ns Sector Erase Architecture - One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout - Eight 4K Word Sectors with Individual Write Lockout Fast Word Program Time - 10 s Typical Sector Erase Time: 32K Word Sectors - 500 ms; 4K Word Sectors - 100 ms Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 10 mA Active - 15 A Standby Data Polling and Toggle Bit for End of Program Detection VPP Pin for Write Protection and Accelerated Program Operations RESET Input for Device Initialization Sector Lockdown Support TSOP Package Top or Bottom Boot Block Configuration Available 128-bit Protection Register Common Flash Interface (CFI) Green (Pb/Halide-free) Packaging
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64-megabit (4M x 16) 3-volt Only Flash Memory AT49BV642D AT49BV642DT
1. Description
The AT49BV642D(T) is a 2.7-volt 64-megabit Flash memory organized as 4,194,304 words of 16 bits each. The memory is divided into 135 sectors for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for in-system programming. To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. The end of program or erase is detected by Data Polling or toggle bit. The VPP pin provides data protection and faster programming times. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 10.0V, the program (dual-word program command) operation is accelerated. A six-word command (Enter Single Pulse Program Mode) to remove the requirement of entering the three-word program sequence is offered to further improve programming time. After entering the six-word code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, by taking the RESET pin to GND or by a highto-low transition on the V PP input. Erase, Erase Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-word code reside in the software of the final product but only exist in external programming code.
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2. Pin Configurations
Pin Name I/O0 - I/O15 A0 - A21 CE OE WE RESET VPP VCCQ Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Reset Write Protection and Power Supply for Accelerated Program Operations Output Power Supply
2.1
TSOP Top View (Type 1)
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE RESET VPP NC A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
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3. Device Operation
3.1 Command Sequences
The device powers on in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. After the completion of a program or an erase cycle, the device enters the read mode. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences.
3.2
Read
The AT49BV642D(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
3.3
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins.
3.4
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical "1". The entire memory can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
3.4.1
Chip Erase Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during Chip Erase except Erase Suspend will be ignored.
3.4.2
Sector Erase As an alternative to a full chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose address is valid at the sixth falling edge of WE will be erased provided the given sector has not been protected.
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3.5
Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The programming address and data are latched in the fourth cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s.
3.6
Sector Lockdown
Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector's usage as a write-protected region is optional to the user. At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed.
3.6.1
Sector Lockdown Detection A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see "Software Product Identification Entry/Exit" sections on page 23), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. Sector Lockdown Override The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.
3.6.2
3.7
Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are don't care. The "Status Bit Table" on page 10 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49BV642D(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, "00" or "01". If the configuration register is set to "00", the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a "01", a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a "00" or to a "01", any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is "00". Using the four-bus cycle set configuration register command as shown in the "Command Definition Table" on page 11, the value of the configuration register can be changed. Voltages applied to the reset pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below.
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3.7.1 Data Polling The AT49BV642D(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a "00", during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see "Status Bit Table" on page 10 for more details. If the status bit configuration register is set to a "01", the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 3-1 and 3-2 on page 8. 3.7.2 Toggle Bit In addition to Data Polling, the AT49BV642D(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see "Status Bit Table" on page 10 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 3-3 and 3-4 on page 9. 3.7.3 Erase/Program Status Bit The device offers a status bit on I/O5 that indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a word program operation has been successfully performed. The device may also output a "1" on I/O5 if the system tries to program a "1" to a location that was previously programmed to a "0". Only an erase operation can change a "0" back to a "1". If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress. Please see "Status Bit Table" on page 10 for more details. VPP Status Bit The AT49BV642D(T) provides a status bit on I/O3 that provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a "1". Once the VPP status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will output a "0". Please see "Status Bit Table" on page 10 for more details.
3.7.4
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3.8
Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same.
3.9
Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same.
3.10
128-Bit Protection Register
The AT49BV642D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the "Command Definition Table" on page 11. To lock out block B, the four-bus cycle lock protection register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. To determine whether block B is locked out, the status of Block B Protection command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the "Protection Register Addressing Table" on page 12 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not or reading the protection register, the Product ID Exit command must be given prior to performing any other operation.
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3.11 Common Flash Interface (CFI)
Common Flash Interface (CFI) is a published, standardized data structure that may be read from a Flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the Flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in the "Common Flash Interface Definition Table" on page 24. To exit the CFI Query mode, the product ID exit command must be given.
3.12
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV642D(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically timeout 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) VPP is less than VILPP.
3.13
Input Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V.
3.14
Output Levels
For the AT49BV642D(T), output high levels are equal to VCCQ - 0.1V (not VCC). For 2.65V to 3.6V output levels, VCCQ must be tied to VCC.
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Figure 3-1.
Data Polling Algorithm (Configuration Register = 00)
Figure 3-2.
Data Polling Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0 Addr = VA
Read I/O7 - I/O0 Addr = VA
YES I/O7 = Data? NO NO
NO I/O7 = 1?
YES NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES Read I/O7 - I/O0 Addr = VA
YES Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Write Product ID Exit Command
I/O7 = Data?
YES
NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode
Note:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
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Figure 3-3. Toggle Bit Algorithm (Configuration Register = 00) Figure 3-4. Toggle Bit Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
YES Read I/O7 - I/O0 Twice
YES Read I/O7 - I/O0 Twice
Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command
NO
Toggle Bit = Toggle? YES
NO
Program/Erase Operation Successful, Device in Read Mode
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful, Write Product ID Exit Command
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
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4. Status Bit Table
Status Bit I/O7 Configuration Register Programming Erasing Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector Erase Suspended & Program Non-erasing Sector Erase Suspended & Program Suspended and Reading from Non-suspended Sectors Program Suspended & Read Programming Sector Program Suspended & Read Non-programming Sector Notes: 00 I/O7 0 1 DATA I/O7 I/O7 01 0 0 1 DATA 0 I/O6 00/01 TOGGLE TOGGLE 1 DATA TOGGLE I/O5(1) 00/01 0 0 0 DATA 0 I/O3(2) 00/01 0 0 0 DATA 0 I/O2 00/01 1 TOGGLE TOGGLE DATA TOGGLE
DATA
DATA
DATA
DATA
DATA
DATA
I/O7 DATA
1 DATA
1 DATA
0 DATA
0 DATA
TOGGLE DATA
1. I/O5 switches to a "1" when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a "1" when the VPP level is not high enough to successfully perform program and erase operations.
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5. Command Definition Table
1st Bus Cycle Command Sequence Read Chip Erase Sector Erase Word Program Dual-Word Program
(4)
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
Bus Cycles 1 6 6 4 5 6 1 6 1 1 3 3 1 4 4 4 4 1
Addr Addr 555 555 555 555 555 Addr 555 xxx xxx 555 555 xxx 555 555 555 555 X55
Data DOUT AA AA AA AA AA DIN AA B0 30 AA AA F0(8) AA AA AA AA 98
AAA(2) AAA AAA AAA AAA
55 55 55 55 55
555 555 555 555 555
80 80 A0 E0 80
555 555 Addr Addr0 555
AA AA DIN DIN0 AA
AAA AAA
55 55
555 SA
(3)
10 30
Addr1 AAA
DIN1 55 555 A0
Enter Single-pulse Program Mode Single-pulse Word Program Mode Sector Lockdown(5) Erase/Program Suspend Erase/Program Resume Product ID Entry Product ID Exit
(6)
AAA
55
555
80
555
AA
AAA
55
SA(3)(5)
60
AAA AAA
55 55
555 555
90 F0(8)
(7)
Product ID Exit(7) Program Protection Register - Block B Lock Protection Register - Block B Status of Block B Protection Set Configuration Register CFI Query
AAA AAA AAA AAA
55 55 55 55
555 555 555 555
C0 C0 90 D0
Addr(9) 80 80 xxx
DIN X0 DOUT(10) 00/01(11)
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don't Care). 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 13 - 16 for details). 4. The fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used for manufacturing purpose only. 5. Once a sector is in the lockdown mode, the data in the protected sector cannot be changed, unless the chip is reset or power cycled. 6. During the fourth bus cycle, the manufacturer code is read from address 00000H, the device code is read from address 00001H, and the data in the protection register is read from addresses 000081H - 000088H. 7. Either one of the Product ID Exit commands can be used. 8. Bytes of data other than F0 may be used to exit the product ID mode. However, it is recommended that F0 be used. 9. Any address within the user programmable register region. Please see "Protection Register Addressing Table" on page 12. 10. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 11. The default state (after power-up) of the configuration register is "00".
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6. Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages Except VPP (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V VPP Input Voltage with Respect to Ground ......................................... 0V to 10.0V All Output Voltages with Respect to Ground ...........................-0.6V to VCCQ + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7. Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
All address lines not specified in the above table must be "0" when accessing the protection register, i.e. A21 -A8 = 0.
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8. Memory Organization - AT49BV642D
x16 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF
8. Memory Organization - AT49BV642D (Continued)
x16 Sector SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF
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8. Memory Organization - AT49BV642D (Continued)
x16 Sector SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 - 29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF
8. Memory Organization - AT49BV642D (Continued)
x16 Sector SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3FFFFF
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9. Memory Organization - AT49BV642DT
x16 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K
9. Memory Organization - AT49BV642DT (Continued)
x16 Address Range (A21 - A0) 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF
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9. Memory Organization - AT49BV642DT (Continued)
x16 Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 -29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF
9. Memory Organization - AT49BV642DT (Continued)
x16 Sector SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K Address Range (A21 - A0) 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3F8FFF 3F9000 - 3F9FFF 3FA000 - 3FAFFF 3FB000 - 3FBFFF 3FC000 - 3FCFFF 3FD000 - 3FDFFF 3FE000 - 3FEFFF 3FF000 - 3FFFFF
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10. DC and AC Operating Range
AT49BV642D(T) - 70 Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 2.7V - 3.6V
11. Operating Modes
Mode Read Program/Erase(3) Standby/Program Inhibit CE VIL VIL VIH X Program Inhibit X X Output Disable Reset Software Product Identification Notes: 1. 2. 3. 4. 5. 6. X X OE VIL VIH X
(2)
WE VIH VIL X VIH X X X X
RESET VIH VIH VIH VIH VIH X VIH VIL VIH
VPP(1) X(2) VIHPP(4) X X X VILPP(5) X X
Ai Ai Ai X
I/O DOUT DIN High Z
X VIL X VIH X
High Z X A0 = VIL, A1 - A21 = VIL A0 = VIH, A1 - A21 = VIL High Z Manufacturer Code(6) Device Code(6)
The VPP pin can be tied to VCC. For faster program operations, VPP can be set to 9.5V 0.5V. X can be VIL or VIH. Refer to program cycle waveforms on page 21. VIHPP (min) = 1.65V. VILPP (max) = 0.4V. Manufacturer Code: 001FH; Device Code: 01D6H - AT49BV642D; 01D2H - AT49BV642DT.
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12. DC Characteristics
Symbol ILI ILO ISB ICC(1) ICC1 VIL VIH VOL VOH Note: Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Read Current VCC Programming Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1. In the erase mode, ICC is 25 mA. IOL = 2.1 mA IOH = -100 A VCCQ - 0.1 VCCQ - 0.6 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCCQ - 0.3V to VCC f = 5 MHz; IOUT = 0 mA 15 10 Min Typ Max 2 2 25 15 25 0.6 Units A A A mA mA V V V V
13. Input Test Waveforms and Measurement Level
2.0V AC DRIVING LEVELS 0.6V 1.5V AC MEASUREMENT LEVEL
tR, tF < 5 ns
14. Output Test Load
VCCQ 1.8K OUTPUT PIN 1.3K
30 pF
15. Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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16. AC Read Characteristics
Symbol tRC tACC tCE tOE tDF tOH tRO Parameter Read Cycle Time Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid CE, OE High to Data Float Output Hold from OE, CE or Address, whichever Occurs First RESET to Output Delay 0 100 Min 70 70 70 20 25 Max Units ns ns ns ns ns ns ns
17. Asynchronous Read Cycle Waveform(1)(2)(3)
tRC A0 - A21 ADDRESS VALID
CE
tCE OE tOE tDF tACC tRO HIGH Z OUTPUT VALID tOH
RESET
I/O0 - I/O15
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
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18. AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tWPH tDS tDH, tOEH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Write Pulse Width High Data Setup Time Data, OE Hold Time Min 0 25 0 0 25 15 25 0 Max Units ns ns ns ns ns ns ns ns
19. AC Word Load Waveforms
19.1 WE Controlled
19.2
CE Controlled
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20. Program Cycle Characteristics
Symbol tBP tBPD tAS tAH tDS tDH tWP tWPH tWC tRP tEC tSEC1 tSEC2 tES tPS Parameter Word Programming Time Word Programming Time in Dual Programming Mode Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Reset Pulse Width Chip Erase Cycle Time Sector Erase Cycle Time (4K Word Sectors) Sector Erase Cycle Time (32K Word Sectors) Erase Suspend Time Program Suspend Time 0 25 25 0 25 15 70 500 64 0.1 0.5 2.0 6.0 15 10 Min Typ 10 5 Max 120 60 Units s s ns ns ns ns ns ns ns ns seconds seconds seconds s s
21. Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
tAS tAH
555 AAA
tDH
555 ADDRESS 555
A0 - A21
tWC
tDS
AA 55 A0 INPUT DATA AA
DATA
22. Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP tWPH
WE
tAS tAH
555 AAA
tDH
555 555 AAA Note 2
A0-A21
tWC
tDS
AA 55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 Note 3 WORD 5
tEC
DATA
WORD 0
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under "Command Definition Table" on page 11.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
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23. Data Polling Characteristics
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time
0
ns
1. These parameters are characterized and not 100% tested. 2. See tOE spec on page 19.
24. Data Polling Waveforms
WE CE OE I/O7 A0-A21
25. Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time
(2)
Min 10 10
Typ
Max
Units ns ns ns
50 0
ns ns
1. These parameters are characterized and not 100% tested. 2. See tOE spec on page 19.
26. Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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27. Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 90 TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
28. Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA F0 TO ADDRESS 555
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. 2. 3. 4. 5.
Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), and A11 - A21 (Don't Care). A1 - A21 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturer Code: 001FH(x16) Device Code: 01D6H - AT49BV642D; 01D2H - AT49BV642DT. 6. Either one of the Product ID Exit commands can be used.
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29. Common Flash Interface Definition Table
Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Data 0051h 0052h 0059h 0002h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0090h 00A0h 0004h 0002h 0009h 0010h 0004h 0004h 0004h 0004h 0017h 0001h 0000h 0002h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write - 10 s Typ dual-word program time - 5 s Typ sector erase - 500 ms Typ chip erase - 64,300 ms Max word write/typ time Max dual-word program time/typ time Max sector erase/typ sector erase Max chip erase/ typ chip erase Device size x16 device x16 device Max number of bytes in multiple byte write = 4 Max number of bytes in multiple byte write = 4 2 regions, x = 2 8K bytes, Y = 7 8K bytes, Y = 7 8K bytes, Z = 32 8K bytes, Z = 32 64K bytes, Y = 126 64K bytes, Y = 126 64K bytes, Z = 256 64K bytes, Z = 256 Comments "Q" "R" "Y"
24
AT49BV642D(T)
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29. Common Flash Interface Definition Table (Continued)
Address Data Comments VENDOR SPECIFIC EXTENDED QUERY 41h 42h 43h 44h 45h 0050h 0052h 0049h 0031h 0030h "P" "R" "I" Major version number, ASCII Minor version number, ASCII Bit 0 - chip erase supported, 0 - no, 1 - yes Bit 1 - erase suspend supported, 0 - no, 1 - yes Bit 2 - program suspend supported, 0 - no, 1 - yes Bit 3 - simultaneous operations supported, 0 - no, 1 - yes Bit 4 - burst mode read supported, 0 - no, 1 - yes Bit 5 - page mode read supported, 0 - no, 1 - yes Bit 6 - queued erase supported, 0 - no, 1 - yes Bit 7 - protection bits supported, 0 - no, 1 - yes Bit 0 - top ("0") or bottom ("1") boot block device Undefined bits are "0" Bit 0 - 4 word linear burst with wrap around, 0 - no, 1 - yes Bit 1 - 8 word linear burst with wrap around, 0 - no, 1 - yes Bit 2 - continuos burst, 0 - no, 1 - yes Undefined bits are "0" Bit 0 - 4 word page, 0 - no, 1 - yes Bit 1 - 8 word page, 0 - no, 1 - yes Undefined bits are "0" Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register - 2*n # of bytes in the user prog section of prot register - 2*n
46h
0087h
47h
0000h AT49BV642DT or 0001h AT49BV642D
48h
0000h
49h 4Ah 4Bh 4Ch
0000h 0080h 0003h 0003h
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3631A-FLASH-04/06
30. Ordering Information
30.1
tACC (ns)
Green Package (Pb/Halide-free/RoHS Compliant)
ICC (mA) Active Standby Ordering Code AT49BV642D-70TU Package Operation Range Industrial (-40 to 85 C)
70
15
0.025
AT49BV642DT-70TU
48T
Package Type 48T 48-lead, Plastic Thin Small Outline Package (TSOP)
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31. Packaging Information
31.1 48T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 11.90 0.50 NOM - - 1.00 20.00 18.40 12.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 12.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 48T REV. B
R
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32. Revision History
Revision No. Revision A - April 2006 History * Initial Release
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AT49BV642D(T)
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